This invention relates generally to translating information, and more particularly to translating information in a computer storage unit from one form to another.
Many modern computer applications require translation of information from one format to another. For instance, a computer may need to translate a particular webpage from one language to another.
Translation of contents from one form to another usually requires software code to implement the translation. In some computers, translate instructions (TR) may allow software to map a range from a particular memory location from one character value scheme to another character value scheme based on a prearranged mapping table which may be maintained in memory.
Prior art systems and methods typically make use of either specialized hardware to process the entire translate instruction or, in a millicode capable system, specialized millicode instruction routines may be used to implement such an instruction.
As the instruction set for high-end processors has evolved over the years, more and more complex instructions and features have been added to the architecture. Conceptually more straightforward instructions, such as loads, stores, moves, branches, and logical and arithmetic instructions, can be implemented directly by the hardware. The more complex instructions and features, such as I/O instructions, Start Interpretive Execution (SIE), cross-memory instructions, interruption handlers, resets, and certain RAS (reliability, availability, and serviceability) features, are typically implemented with some type of internal code. One form of such code internal to the central processor (CP) is called millicode, which can implement complex instructions by utilizing preexisting dataflow and hardware controlled execution units of a pipelined processor.
The use of a special coprocessor, e.g., a hardware engine, to perform the mapping from one character value scheme to another character value scheme based on a prearranged mapping table may include time delays related to starting of the hardware engine and potential sub-optimized caching of the mapping table.
In millicode capable systems, millicode assist instructions have been provided as means of assisting millicode to do the character conversion but may require multiplexing of an index register input to the particular address generator. The address generator may be the most critical path in microprocessor design and multiplexing thereof may slow down the particular microprocessor.
It would be beneficial to remove the necessity of specialized hardware engines and to provide a new set of specialized millicode assist instructions to allow a more efficient character mapping as required for TR instructions.